The present invention relates to a semiconductor memory cell, and further to a semiconductor device.
In recent years, many portable apparatuses and/or equipments adopt flash memories for the purpose of high-speed readout operation. For the purpose of achieving the high-speed readout operation, in general, a memory cell array is used, in which memory cells are connected in parallel while one (1) piece of data line contact is provided for every pair of the cells connected in parallel, thereby suppressing parasitic resistance therein down to the minimum, so as to achieve the high-speed readout operation. Such memory cell array itself, however, was already known for many years, and was described, for example, in “Ouyou Butsuri”, by KUME 65, p.1114, (1996).
For the flash memory, it is important to keep the reliability of the memory cells thereof. For keeping the reliability of the memory cells, many technical innovations were made in the manufacturing processes thereof, however no drastic technology was developed up to now. At preset, redundant memory cells are also manufactured in the place thereof, in which a so-called ECC technology or the like is widely adopted, such as, replacing poor quality or defected cells in the circuits, electrically.
With the development of such the portable equipments or apparatuses, including, such as, a PDA, a digital camera, a cellular (mobile) telephone apparatus, etc., for example, as well as, wide spreading of so-called the multi-media, a nonvolatile memory of large capacity comes to be important more and more in the future. In particular, the importance of the semiconductor nonvolatile memory cells, such as the flash memory, being a representative one thereof, is considered from the viewpoints of small-sizing, high-speed accessing, and shock-resistant property thereof. However, while reduction or scaling-down of sizes is proceeded in the horizontal direction on the cells, in accordance with the trends of the manufacturing technology thereof, but scaling-down is hardly done in the vertical direction, i.e., in the direction of the film thickness thereof. This is due to problems on reliability, including, such as, leakage under a low electric field, and so on, and because of this, the certainty is considered on that this short channel effect will come up remarkable in near future. It is also impossible to lower the voltage, in particular of the applied voltage therein, and then the sizes of the peripheral circuits cannot be made small, therefore the space factor of occupying an area of the memory cells on a chip falls down, and since the chip area cannot be made small irrespective of miniaturization thereof, the cost rises up.
Among those problems, various methods are proposed from a viewpoint of the write-in voltage. As the conventional technologies relating thereto, a method of using the secondary electron for injection is known, for example, in J. D. Bude et al., IEEE International Electron Device Meeting 1995, p989-991, 1995, and a method of applying the source-drain electric field for injection with using a step, for example, in S. Ogura et al., IEEE International Electron Device Meeting 1998, p987-990, 1998.
Also, there is other problem thereof, such as, price of the semiconductor nonvolatile memory. At present, comparing with, such as, a hard disc, an opt-magnetic disc, or a 0VD, etc., the price per a unit of memory capacity of the semiconductor memory comes up as several-times high or more as that. Accordingly, the lowering of costs is necessary, however, so-called a multi-value memory technology is put into practical use, wherein information to be memorized into a unit cell is made up of two (2) bits. This means that a large number of levels are prepared through control of the electron number injected into a memory node (i.e., a floating gate). As an example of such the conventional art of the multi-value memory, there is known Jung et al., IEEE International Solid-State Circuit Conference 1996, p32-33, 1996. Also, a technology of memorizing independent information is known, not through the large number of the levels, but dividing the floating gate of one (1) cell into two (2), for example, in IEEE Transactions on Components, Pacing and Manufacturing Technology Part A, Vol. 20, 1997.
The ECC technology is able to lower the demand on the reliability for each unit of memory cells, however for it, since the electronic circuit is put into between them, therefore it means that the times necessary for read-out, write-in and erase operations are sacrificed. Accordingly, in particular for the application requiring a high read-out speed, this ECC technology cannot be applied to, therefore there is a problem that the reliability of cells has a direct influence upon the cost of memory.
The flash memory cell stores electric charge in the floating gate thereof, thereby to memorize information therein, however if there is leakage in any one of those floating gates, the memory cell is a poor quality or defected one. Accordingly, the entire memory device is the poor quality or defected one, including that memory cells therein. Thus, only the leakage in a portion of the floating gates results into the poor quality of the memory cell as a whole, therefore there is a problem that it comes up to the high price directly in manufacturing cost of the memory cell itself.